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dual, 200 ma, low noise, high psrr voltage regulator data sheet adp220/ADP221 rev. h document feedback informati on furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2008 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features input voltage range: 2.5 v to 5.5 v dual independent 200 ma low drop out voltage regulators miniature 6 - ball, 1.0 mm 1. 5 mm wl csp and 6 - b all b umped b are d ie initial accuracy: 1 % stable with 1 f ceramic output capacitors no noise bypass capacit or required two independent l ogic controlled enable s over c urrent and t hermal protection active output pull - down (ADP221) key specifications high psrr 76 db psrr up to 1 k hz 7 0 db psrr at 10 k hz 6 0 db psrr at 100 k hz 4 0 db psrr at 1 mhz low output noise 27 v rms typical output noise at v out = 1.2 v 50 v rms typical output noise at v out = 2.8 v excellent transient response low dropout voltage: 1 5 0 mv @ 200 ma load 6 0 a typical ground current at no load , both ldos enabled 1 0 0 s fast turn - on circuit guarant eed 200 ma output current per regulator ? 40 c to + 125 c junction temperature applications mobile phones digital camera s and audio devices portable and battery - powered equipment portable medical devices post dc - to - dc regulation typical application circuits en1 vout1 gnd vin en2 vout2 top view (not to scale) 1 a b c 2 v out1 = 2.8v 1f 1f 1f v in = 3.3v v out2 = 2.8v 07572-001 off on off on figure 1 . ty pical application circuit thermal shutdown en1 en2 gnd current limit current limit 60 60 reference ADP221 only control logic and enable vin vout1 vout2 adp220 07572-002 figure 2 . block diagram of the adp220/ADP221 general description t he 200 ma dual output adp220/ADP221 combine high psrr , low noise, low quiescent current , and low d ropout voltage in a voltage regulat or ideally suited for wireless applications with demanding performance and board space requirements. the low quiescent current, low dropout voltage , and wide i nput voltage range of the adp220/ADP221 extend the battery life of portable devices. the adp220/a dp221 maintain power supply rejection greater than 6 0 d b for frequencies as high as 100 k hz while operating with a low headroom voltage. the adp220 offers much lower noise performance than competing ldos without the need for a noise bypass capacitor. the a dp221 also includes an active pull - down to quickly discharge output loads . the adp220/ADP221 are available in a miniature 6 - ball wlcsp package and 6 - b all b umped b are d ie and is stable with tiny 1 f 30% ceramic output capacitors, resulting in the smalles t possible board area for a wide variety of portable power needs. the adp220/ADP221 are available i n many output voltage combinations , ranging from 0.8 v to 3.3 v , and offer over cur - rent and thermal protection to prevent damage in adverse conditions .
adp220/ADP221 data sheet rev. h | page 2 of 20 tab le of contents features .............................................................................................. 1 applications ....................................................................................... 1 typical application circuits ............................................................ 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 input and output capacitor, recommended specifications .. 4 absolute maximum ratings ............................................................ 5 thermal data ................................................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ..............................................7 theory of operation ...................................................................... 11 applications information .............................................................. 12 capacitor selection .................................................................... 12 undervoltage lockout ............................................................... 13 enable feature ............................................................................ 13 current - limit and thermal overload protection ................. 14 ther mal considerations ............................................................ 14 printed circuit board (pcb) layout considerations ................ 16 outline dimensions ....................................................................... 17 ordering guide .......................................................................... 18 revision history 1 /1 3 rev. g to rev. h change s to undervoltage lockout input voltage rising parameter and undervoltage lockout input voltage falling parameter, table 1 ............................................................................. 3 11 /12 rev. f to rev. g added 6 - ball bumped bare die ( cd - 6 - 7 ) ...................... universal change to undervoltage lockout input voltage rising parameter, table 1 ............................................................................. 3 updated outline dimensions ....................................................... 17 moved ordering guide .................................................................. 18 4 /12 rev. e to rev. f changes to ordering guide .......................................................... 17 1 1 /1 0 rev. d to rev. e changes to ordering guide .......................................................... 17 5/10 rev. c to rev. d changes to figure 1 .......................................................................... 1 changes to ordering guide .......................................................... 17 1/ 1 0 rev. b to rev. c changes to figure 24 ...................................................................... 10 10 /09 rev . a to rev . b changes to features section ............................................................ 1 changes to table 3 and table 4 ........................................................ 5 changes to figure 4, figure 6, figure 7, and figure 9 .................. 7 changes to figure 10 and figure 12 ............................................... 8 changes to figure 17 ......................................................................... 9 changes to figure 25 ...................................................................... 10 changes to enable feature section and figure 32 ..................... 13 changes to current - limit and thermal overland protection section and thermal considerations section ............................ 14 changes to ordering guide .......................................................... 17 3/09 rev. 0 to rev. a changes to figure 15 ......................................................................... 8 changes to figure 16 ......................................................................... 9 changes to ordering guide .......................................................... 17 10 /08 revision 0: initial version
data sh eet adp220/ADP221 rev. h | page 3 of 20 specifications v in = (v out + 0.5 v) or 2. 5 v (whicheve r is greater), en 1 = en2 = v in , i out 1 = i out2 = 1 0 m a , c in = c out 1 = c out2 = 1 f , t a = 25c , unless otherwise noted. table 1 . parameter symbol conditions min typ max unit input voltage range v in t j = ?40c to +125c 2.5 5.5 v operating supply current with both regulators on i gnd i out = 0 a 6 0 a i out = 0 a, t j = ?40c to +125c 120 a i out = 10 ma 7 0 a i out = 10 ma, t j = ?40c to +125c 1 40 a i out = 200 ma 120 a i out = 200 ma, t j = ?40c to +125c 220 a shutdown current i gnd - sd en1= en2 = gnd 0. 1 a en1= en2 = gnd, t j = ?40c to +125c 2 a fixed output voltage accuracy v out ? 1 + 1 % 100 a < i out < 200 ma, v in = (v out + 0.5 v) to 5.5 v, t j = ?40c to +125c ? 2 +2 % line regulation ? v out /?v in v in = (v out + 0.5 v) to 5.5 v 0.01 %/v v in = (v out + 0.5 v) to 5.5 v, t j = ?40c to +125c ? 0.0 3 +0.0 3 %/v load regulation 1 ? v out /?i out i out = 1 ma to 200 ma 0.001 %/ma i out = 1 ma to 200 ma, t j = ?40c to +125c 0.003 %/ma dropo u t v o ltage 2 v dropout v out = 3.3 v mv i out = 10 ma 7.5 mv i out = 10 ma, t j = ?40c to +125c 12 mv i out = 200 ma 150 mv i out = 200 ma, t j = ?40c to +125c 2 3 0 mv start - up time 3 t start - up v out = 3.3 v , both initially off, e nable one 240 s v out = 0.8 v , both initially off, enable one 100 s v out = 3.3 v, one initially on, e nable second 180 s v out = 0.8 v , one initially on, enable second 20 s active pull - down resistance t shutdown v out = 2.8 v, r load = , c out = 1 f , ADP221 only 80 current - limit threshold 4 i limit 240 300 440 ma thermal shutdown thermal shutdown threshold ts sd t j rising 155 c thermal shutdown hysteresis ts sd - hys 15 c en input en input logic high v ih 2.5 v v in 5.5 v 1. 2 v en input logic low v il 2.5 v v in 5.5 v 0.4 v en input leakage current v i- leakage en1 = en2 = v in or gnd 0.1 a en1 = en2 = v in or gnd, t j = ?40c to +125c 1 a undervoltage lockout uvlo input voltage rising uvlo rise 2.45 v input voltage falling uvlo fal l 2.2 2.35 v hysteresis uvlo hys 100 mv output noise out noise 10 hz to 100 khz, v in = 5 v, v out = 3.3 v 56 v rms 10 hz to 100 khz, v in = 5 v, v out = 2.8 v 50 v rms 10 hz to 100 khz, v in = 3.6 v, v out = 2.5 v 45 v rms 10 hz to 100 khz, v in = 3.6 v, v out = 1.2 v 27 v rms
adp220/ADP221 data sheet rev. h | page 4 of 20 parameter symbol conditions min typ max unit power supply rejection ratio psrr v in = 2.5 v, v out = 0.8 v, i out = 100 ma 100 hz 76 db 1 khz 76 db 10 khz 70 db 100 khz 60 db 1 mhz 40 db v in = 3.8 v, v out = 2.8 v, i out = 100 ma 100 hz 68 db 1 khz 68 db 10 khz 68 db 100 khz 60 db 1 mhz 40 db 1 based on an end - point calculation using 1 ma and 200 ma loads. 2 dropout voltage is defined as the input - to - output voltage dif f erential whe n the input voltage is set to the nominal output voltage. this appl ies only for output voltages above 2.5 v. 3 start - up time is defin ed as the time between the rising edge of enx to v outx being at 90% of its nominal value. 4 current - limit threshold is defi ned as the current at which the output voltage drops to 90% of the specified typical value. for example, the current limit fo r a 3.0 v output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 v, or 2.7 v. input and output cap acitor, recommended specifications table 2 . parameter symbol conditions min typ max uni t minimum input and output capacitance 1 c min t a = ?40c to +125c 0.70 f capacitor esr r esr t a = ?40c to +125c 0.001 1 1 the minimum input and output capacitance should be greater than 0. 7 0 f over the full range of operating conditions. the full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specificati on is met. x7r and x5r type capacitors are recommended ; y5v and z5u capacitors are not recommended for use with ldos.
data sh eet adp220/ADP221 rev. h | page 5 of 20 absolute maximum rat ings table 3 . parameter rating v in to gnd C 0. 3 v to + 6 .5 v v out 1, v out2 to gnd C 0. 3 v to v in en 1, en2 to gnd C 0. 3 v to + 6 .5 v storage temperature range C 65c to +150c operating junction temperature range C 40c to +125c soldering conditions jedec j - std -020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device r eliability. t hermal d ata absolute maximum ratings apply individually only, not in combination. the adp220/ADP221 can be damaged when the junction temperature limits are exceeded. monitoring ambient temper - ature does not guarantee that the junction temper ature ( t j ) is within the specified temperature limits. in applications with high power dissipation and poor thermal resistance, the max i mum ambient temperature may have to be derated. in applications with moderate power dissipation and low pcb thermal re sistance, the maximum ambient temperature can exceed the maximum limit as long as the junction tempera ture is within specification limits. the junction temperature (t j ) of the device is dependent on the ambient temperature (t a ), the po wer dissipation of t he device (p d ) , and the junction - to - ambien t thermal resistance of the package ( ja ). maximum junction temperature (t j ) is calculated from the ambient temperature (t a ) and power dissipation (p d ) using the following formula : t j = t a + ( p d ja ) junction - to - ambient thermal resistance ( ja ) of the package is based on modeling and ca lculation using a 4 - layer board. the junction - to - ambient thermal resistance is highly dependent on the application and board layout. in applications where high maximum power dissipation exists, close attention to thermal board design is required. the valu e of ja may vary, depending on pcb material, layout, and environmental conditions. the specified values of ja are based on a four - layer, 4 inch 3 inch , circuit board. refer to jedec jesd 51 - 9 for detailed informa - tion on the board construction. for ad ditional information, see the an - 617 application note , microcsp tm wafer level chip scale package . jb is the junction - to - board thermal characterization parameter with units of c / w. jb of the package is based on modeling and calculation using a 4 - layer b oard. the jesd51 - 12, guidelines for reporting and using package thermal information , states that thermal characterization parameters are not the same as thermal resistances. jb measures the component power flowing through multiple thermal paths rather th an a single path as in thermal resistance, jb . therefore, jb thermal paths include convection from the top of the package as wel l as radiation from the package. factors that make jb more useful in real - world applications. maximum junction temperature ( t j ) is calculated from the board temperature (t b ) and power dissipation (p d ) using the following formula : t j = t b + ( p d jb ) r efer to jedec jesd51 - 8 and jesd51 - 12 for more detailed information on jb . thermal resistance ja and jb are specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 4 . package type ja jb unit 6 - ball, 0.5 mm pitch wlcsp 260 43.8 c/w 6 - ball bumped bare die 260 43.8 c/w esd caution
adp220/ADP221 data sheet rev. h | page 6 of 20 pin configuration an d function descripti ons top view (ball side down) not to scale 07572-003 1 a 2 en1 vout1 gnd vin en2 vout2 b c figure 3. pin configuration table 5 . pin function descriptions pin no. mnemonic description a1 en1 enable input for regulator 1 . drive en1 high to turn on r egulator 1 ; drive it low to turn off regulator 1 . for automatic startup, connect en1 to vin. b1 gnd ground pin. c1 en2 enable input for regulator 2 . drive en2 high to turn on r egulator 2 ; drive it low to turn off regulator 2 . for automatic startup, co nnect en2 to vin . a2 vout1 regulated output voltage 1 . connect a 1 f or greater output capacitor between vout1 and gnd. b2 vin regulator input supply. bypass vin to gnd with a 1 f or greater capacitor. c2 vout2 regulated output voltage 2 . connect a 1 f or greater output capacitor between vout2 and gnd.
data sh eet adp220/ADP221 rev. h | page 7 of 20 typical performance characteristics v in = 3.3 v, v out1 = v out 2 = 2 .8 v, i out = 10 ma, c in = c out 1 = c out2 = 1 f, t a = 25c, unless otherwise noted. 2.85 2.83 2.81 2.79 2.77 output voltage (v) junction temperature (c) 2.75 ?40 ?5 25 85 125 i load = 10a i load = 100a i load = 1ma i load = 10ma i load = 100ma i load = 200ma 07572-004 figure 4. output volta ge vs. junction temperature 2.85 2.83 2.81 2.79 2.77 output voltage (v) load current (ma) 2.75 0.01 0.1 1 10 100 1k v out = 2.8v v in = 3.3v t a = 25c 07572-005 figure 5 . output voltage vs. load current 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 input voltage (v) v out = 2.8v t a = 25c i load = 10a i load = 100a i load = 1ma i load = 10ma i load = 100ma i load = 200ma 2.85 2.83 2.81 2.79 2.77 output voltage (v) 2.75 07572-006 figure 6 . output voltage vs. input voltage 140 120 100 80 60 40 20 ground current (a) junction temperature (c) 0 ?40 ?5 25 85 125 i load = 10a i load = 100a i load = 1ma i load = 10ma i load = 100ma i load = 200ma 07572-007 figure 7 . ground current vs. junction temperature , singl e output loaded 120 100 80 60 40 20 ground current (a) 0 v out = 2.8v v in = 3.3v t a = 25c load current (ma) 0.01 0.1 1 10 100 1k 07572-008 figure 8 . ground current vs. load current , single output loaded 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 input voltage (v) 120 100 80 60 40 20 ground current (a) 0 i load = 10a i load = 100a i load = 1ma i load = 10ma i load = 100ma i load = 200ma 07572-009 figure 9 . ground current vs. input voltage , single output loaded
adp220/ADP221 data sheet rev. h | page 8 of 20 160 140 120 100 80 60 40 20 ground current (a) junction temperature (c) 0 ?40 ?5 25 85 125 i load = 10a i load = 100a i load = 1ma i load = 10ma i load = 100ma i load = 200ma 07572-010 figure 10 . ground curren t vs. junction temperature, both outputs loaded 140 120 100 80 60 40 20 ground current (a) 0 load currrent (ma) 0.01 0.1 1 10 100 1k v out = 2.8v v in = 3.3v t a = 25c 07572-011 figure 11 . ground current vs. load current, both outputs loaded 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 input voltage (v) 140 120 100 80 60 40 20 ground current (a) 0 i load = 10a i load = 100a i load = 1ma i load = 10ma i load = 100ma i load = 200ma 07572-012 figure 12 . ground current vs. input voltage, both outputs loaded ?50 ?25 125 100 75 50 25 0 temperature (c) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 shutdown current (a) 0 3.3v 3.6v 4.0v 4.3v 4.9v 5.5v 07572-013 figure 13 . shutdown current vs. temperature at various input voltages 1 10 100 1k load current (ma) 250 200 150 100 50 dropout voltage (mv) 0 2.5v 2.8v 3.3v 07572-014 figure 14 . dropout voltage vs. load current and output voltage 2.6 2.7 2.8 2.9 3.0 3.1 input voltage (v) 2.90 2.85 2.80 2.75 2.70 2.65 2.60 2.55 2.50 2.45 output voltage (v) 2.40 i load = 1ma i load = 5ma i load = 10ma i load = 50ma i load = 100ma i load = 200ma 07572-015 figure 15 . output voltage vs. input voltage (in dropout)
data sh eet adp220/ADP221 rev. h | page 9 of 20 2.6 2.7 2.8 2.9 3.0 3.1 input voltage (v) 180 120 140 160 100 80 60 40 20 ground current (a) 0 i load = 1ma i load = 5ma i load = 10ma i load = 50ma i load = 100ma i load = 200ma 07572-016 figure 16 . ground current vs. input voltage (in dropout) 10 100 1k 10k 100k 1m 10m frequency (hz) ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 psrr (db) ?110 v ripple = 50mv v in = 3.8v v out = 2.8v c out = 2.2f 200ma 100ma 10ma 1ma 100a 07572-017 figure 17 . power supply rejection ratio vs. frequency , 2.8 v 10 100 1k 10k 100k 1m 10m frequency (hz) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 psrr (db) ?100 v ripple = 50mv v in = 4.3v v out = 3.3v c out = 1f 200ma 100ma 10ma 1ma 100a 07572-018 figure 18 . power supply rejection ratio vs. frequen cy , 3.3 v 10 100 1k 10k 100k 1m 10m frequency (hz) ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 psrr (db) ?110 ?100 v ripple = 50mv v in = 2.5v v out = 0.8v c out = 1f 200ma 100ma 10ma 1ma 100a 07572-019 figure 19 . power supply rejection ratio vs. frequency , 0.8 v 10 100 1k 10k 100k 1m 10m frequency (hz) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 psrr (db) ?100 3.3v/200ma 0.8v/200ma 1.8v/200ma 3.3v/100a 0.8v/100a 1.8v/100a 07572-020 figure 20 . power supply rejection ratio vs. frequency, at various output voltages and load currents 10 100 1k 10k 100k frequency (hz) 10 0.1 1 output noise spectrum (v/ hz) 0.01 3.3v v/ hz 2.8v v/ hz 0.8v v/ hz 07572-021 figure 21 . output noise spectrum, v in = 5 v, i load = 10 ma
adp220/ADP221 data sheet rev. h | page 10 of 20 0.001 0.01 0.1 1 10 100 1k load current (ma) 60 50 40 30 20 10 noise (v rms) 0 3.3v 2.8v 1.8v 0.8v 07572-022 figure 22 . output noise vs. load current and output voltage, v in = 5 v ch1 200ma b w ch2 50.0mv b w ch3 10.0mv b w m40.0s a ch1 132ma t 10.00% 1 2 3 i load1 v out1 v out2 i load1 = 1ma to 200ma, i load2 = 1ma t 07572-023 figure 23 . load transient response , i load1 = 1 ma to 200 ma, i load 2 = 1 ma ch1 = i load1 , ch2 = v out1 , ch3 = v out2 t ch1 200ma b w ch2 50.0mv b w ch3 10.0mv b w m40.0s a ch1 132ma t 10.00% 1 2 3 i load1 v out1 v out2 i load1 = 1ma to 200ma, i load2 = 100ma 07572-024 figure 24 . load transient response, i load1 = 1 ma to 200 ma, i load2 = 100 ma, ch1 = i load1 , ch2 = v out1 , ch3 = v out2 ch1 1.00v b w ch2 5.00mv b w ch3 5.00mv b w m20.0s a ch1 4.46v t 13.60% 2 1 3 v in v out1 v out2 v in = 4v to 5v, i load1 = 200ma, i load2 = 100ma t 07572-025 figure 25 . line transient respo nse , v in = 4 v to 5 v, i load1 = 200 ma, i load2 = 100 ma ch1 = v in , ch2 = v out1 , ch3 = v out2 ch1 1.00v b w ch2 5.00mv b w ch3 5.00mv b w m20.0s a ch1 4.46v t 10.00% 2 1 3 v in v out1 v out2 v in = 4v to 5v, i load1 = 200ma, i load2 = 1ma t 07572-026 figure 26 . line transient response v in = 4 v to 5 v, i load1 = 200 ma, i load2 = 1 ma ch1 = v in , ch2 = v out1 , ch3 = v out2 ch1 5.00v b w ch2 2.00v b w ch3 2.00v b w m40.0s a ch1 2.10v t 9.80% 2 1 3 t 07572-027 figure 27 . shutdown response, ADP221
data sh eet adp220/ADP221 rev. h | page 11 of 20 theory of operation the adp220/ADP221 are low quiescent current, low dro p out linear regulators that operate from 2.5 v to 5.5 v and provide up to 20 0 ma of current from each o utput . drawing a low 120 a quiescent current (typical) at full load make s the adp220/ ADP221 ideal for battery - operated portable equipment. shut - down current consumption is typically 1 00 na. optimized for use with small 1 f ceramic capacitors, the adp220/ADP221 provide excellent transient performance. thermal shutdown en1 en2 gnd current limit current limit 60 60 reference ADP221 only control logic and enable vin vout1 vout2 adp220 07572-028 figure 28 . internal block diagram internally, the adp220/ADP221 consist of a reference, two error amplifier s, two feedback voltage divider s , and two pmos pass transistor s . output current is delivered via the pmos pass device, which is controlled by the error amplifier. the error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. if the feedback voltage is lower than the reference voltage, the g ate of the pmos device is pulled lower, allowing more current to flow and increasing the output voltage. if the feedback voltage is higher than the reference voltage, the gate of the pmos device is pulled higher, allowing less current to flow and decreasin g the output voltage. th e ADP221 also includes an active pull - down circuit to rapi dly discharge the output load capacitance when each output is disabled. the adp220/ADP221 are available in multiple outpu t voltage options ranging from 0.8 v to 3.3 v. the ad p220/ADP221 use the en1/en2 pin s to enable and disable the vout 1/vout2 pin s under normal operating conditions. when en 1/en2 are high, vout 1/vout2 turn on ; when en 1/en2 are low, vout 1/ vout2 turn off. for automatic startup, en 1/en2 can be tied to vin .
adp220/ADP221 data sheet rev. h | page 12 of 20 ap plications informati on capacitor selection output capacitor the adp220/ADP221 are designed for operation with small, space - saving ceramic capacitors, but the parts function with most commonly used capacitors as long as care is taken with regard s to the ef fective series resistance (esr) value. the esr of the output capacitor affects stability of the ldo control loop. a minimum of 0.70 f capacitance with an esr of 1 ? or less is recommended to ensure stability of the adp220/ADP221 . transient response to c hanges in load current is also affected by output capacitance. using a larger value of output capacitance i mproves the transient response of the adp220/ADP221 to la rge changes in the load current. figure 29 and figure 30 show the transient responses for output capacitance values of 1 f and 4.7 f, respectively. 2 1 3 ch1 200ma b w ch2 50.0mv b w ch3 10.0mv b w m200ns a ch1 132ma t 26.60% t i load1 = 1ma to 200ma, i load2 = 1ma i load1 v out1 v out2, c out = 1f 07572-029 figure 29 . output transient respons e i load1 = 1 ma to 200 ma, i load2 = 1 ma ch1 = i load1 , ch2 = v out1 , ch3 = v out2 , c out = 1 f 2 1 3 ch1 200ma b w ch2 50.0mv b w ch3 10.0mv b w m1.00s a ch1 132ma t 11.40% t i load1 = 1ma to 200ma, i load2 = 1ma i load1 v out1 v out2, c out = 4.7f 07572-030 figure 30 . output transient response i load1 = 1 ma to 200 ma, i load2 = 1 ma ch1 = i load1 , ch2 = v out1 , ch3 = v out2 , c out = 4.7 f input bypass capacitor connecting a 1 f capacitor from vin to gnd reduces the circui t sensitivity to the pcb layout, especially when long input traces or high source impedance are encountered. if an output capacitance greater than 1 f is required, the input capacitor should be increased to match it. input and output capacitor properties any good quality ceramic capacitor can be used with the adp220 / ADP221 , as long as the capacitor meet s the minimum capacit - ance and maximum esr requirements. ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. capacitors must have an adequate dielectric to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are recommended. y5v and z5u dielectrics are not recommended, due to their poor temperature and dc bias characteristics. figure 31 depicts the capacitance vs. voltage bias characteristic of an 0402 1 f, 10 v, x5r capacitor. the voltage stabilit y of a capacitor is strongly influenced by the capacitor size and voltage rating. in general, a capacitor in a larger package or higher voltage rating exhibits better stability. the temperature variation of t he x5r dielectric is about 15% over the ?40c to +85c tempera - ture range and is not a function of the package or voltage rating. 1.2 1.0 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 voltage (v) capacitance (f) 07572-031 figure 31 . capacitance vs. voltage bias characteristic
data sh eet adp220/ADP221 rev. h | page 13 of 20 equation 1 can be used to determine the w orst - case capacitance accounting for capacitor va riation over temperature, compo - nent tolerance, and voltage. c eff = c bias (1 ? tempco ) (1 ? tol ) (1) where: c bias is the effective capacitance at the operating voltage. tempco is the worst - case capacitor temperature coefficient. tol is the worst - case component tolerance. in this example, tempco over ?40c to +85 c is assumed to be 15% for an x5r dielectric. tol is assumed to be 10%, and c bias is 0.94 f at 1.8 v from the graph in figure 31. substituting these values in to equation 1 yields c eff = 0.94 f (1 ? 0.15) (1 ? 0.1) = 0.719 f therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the ldo over temperature and tolerance at the chos en output voltage. to guarantee the performance of the adp220/ADP221 , it is imperative that the effects of dc bias, temperature, and toler - ances on the behavior of the capacitors be evaluated for each application. undervoltage lockout the adp220/ADP221 ha v e an internal undervoltage lockout circuit that disables all inputs and the output when the input voltage is less than approximately 2.2 v. this ensures that the inputs of the adp220/ADP221 and the output behave in a predictable manner during power - up. ena ble feature the adp220/ADP221 use the en x pin s to enable and disable the vout x pin s under normal operating conditions. figure 32 shows a rising voltage on en x crossing the active threshold, then v out x turns on. when a falling voltag e on en x crosses the inactive threshold, v out x turns off. 1 ch1 500mv b w ch2 500mv b w m10.0ms a ch2 1.76v t 27.40% t 07572-032 enx v outx figure 32 . typical en x pin operation as shown in figure 32 , the en x pin s ha ve built - in hysteresis. this prevents on/off oscillations that can o ccur due to noise on the en x pin s as it passes through the threshold points. the active/inactive thresholds of the en x pin s are derived from the vin voltage. therefore, these thresholds vary with changing input voltage. figure 33 shows typical en x active/inactive thre sh - o lds when t he input voltage varies from 2.5 v to 5.5 v. 2.5 3.0 3.5 4.0 4.5 5.0 5.5 input voltage (v) 1.00 0.95 0.90 0.85 0.80 0.75 0.70 0.65 enx pins threshold (v) 0.60 en inactive en active 07572-033 figure 33 . typical en x pin s thresholds vs. input voltage the adp220/ADP221 utilize an internal soft start to limit the inrush curr ent when the output is enabled. the start - up time for the 2 .8 v option is approximately 22 0 s from the time the en x active threshold is crossed to when the output reaches 90% of its final value. the s tart - up time is somewhat depende nt on the output voltag e setting and increases slightly as the output voltage increases. 1 ch1 5.00v b w ch2 2.00v b w m40.0s a ch1 2.10v t 9.80% t ch3 2.00v b w 2 3 07572-034 figure 34 . typical start - up time
adp220/ADP221 data sheet rev. h | page 14 of 20 current - limit and thermal ov erload protection the adp220/ADP221 are protected against damage due to excessive power dissipation b y current and thermal overload protection circuits. the adp220/ADP221 are designed to current limit when the output load reaches 300 ma (typical). when the output load exceeds 300 ma, the output voltage is reduced to maintain a constant current limit. ther mal overload protection is built - in, which limits the junction temperature to a maximum of 15 5 c (typical). under extreme conditions (that is, high ambient temperature and power dissipation) when the junction temperature starts to rise above 15 5 c, the ou tput is turned off, reducing the output current to zero. when the junction temperature drops below 1 40 c, the output is turned on again and the output current is restored to its nominal value. consider the case where a hard short from vout x to gnd occurs. at first, the adp220/ADP221 current limit, so that only 300 ma is conducted into the short. if self - heating of the junc tion is great enough to cause its temperature to rise above 15 5 c, thermal shutdown activates , turning off the output and reducing the o utput current to zero. as the junction tempera ture cools and drops below 140 c, the output turns on and conducts 300 ma into the short, again causing the junction temperature to rise above 15 5 c. this thermal oscillation between 140 c and 155 c causes a c urrent oscillation between 0 ma and 300 ma that continues as long as the short remains at the output. current and thermal limit protections are intended to protect the device against accidental overload conditions. for reliable operation, device power diss ipation must be externally limited so that junction temperatures do not exceed 125c. thermal consideratio ns in most applications, the adp220/ADP221 do not dissipate much heat due to high efficiency. however, in applications with a high ambient temperature and high supply voltage to output voltage differential, the heat dissipated in the package is large enough that it can cause the junction temperature of the die to exceed the maximum junction temperature of 125c. when the junction temperature exceeds 1 55 c, the converter enters thermal shutdown. it recovers only after the junction temper ature has decreased below 140 c to prevent any permanent damage. therefore, thermal analysis for the chosen application is very important to guarantee reliable performan ce over all conditions. the junction temperature of the die is the sum of the ambient temperature of the environment and the tempera - ture rise of the package due to the power dissipation, as shown in equation 2. to guarantee reliable operation, the juncti on temperature of the adp220/ADP221 must not exceed 125c. to ensure that the junction temperature stays below this maximum value, the u ser needs to be aware of the parameters that contribute to junction temperature changes. these parameters include ambi ent tem - pe rature, power dissipation in the power device, and thermal resistances between the junction and ambient air ( ja ). the ja number is dependent on the package assembly compounds used and the amount of copper to which the gnd pins of the package are soldered on the pcb. table 6 shows typical ja values for the adp220/ADP221 for various pcb copper sizes. table 6 . typical ja values copper size (mm 2 ) adp220/adp22 1 (c/w) 0 1 200 50 119 100 118 300 115 500 113 1 device soldered to minimum size pin traces. the junction temperature of the adp220/ADP221 can be calculated from the following equation: t j = t a + ( p d ja ) (2) where: t a is the ambient temperature. p d is the power dissipation in the die, given by p d = [( v in ? v out ) i load ] + ( v in i gnd ) (3) where: i load is the load current. i gnd is the ground current. v in and v out are input and output voltages, respectively. power dissipation due to ground current is quite small and can be ignored. therefore, the junction temperature equation simplifies to t j = t a + { [( v in ? v out ) i load ] ja } (4) as shown in equation 4, for a given ambient temperature, input - to - output voltage differential, and continuous load current, there exists a minimum copper size re quirement for the pcb to ensure the junction temperature does not rise above 125c. figure 35 to figure 39 show junction temperature calculations for different ambient temperatures, total power dissipa tion , and areas of pcb copper. in cases where the board temperatu re is known, the thermal characterization parameter, jb , can be used to estimate the junction temperature rise. t j is calculated from t b and p d using the formula t j = t b + ( p d jb ) (5) the typical jb v alue for the 6 - ball wlcsp is 43.8 c / w.
data sh eet adp220/ADP221 rev. h | page 15 of 20 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 total power dissipation (w) 145 35 45 55 65 75 85 95 105 115 125 135 junction temperature (c) 25 500mm 2 50mm 2 0mm 2 t jmax 07572-035 figure 35 . junction temperature vs . total power dissipation, t a = 25c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 total power dissipation (w) 140 60 70 80 90 100 110 120 130 junction temperature (c) 50 500mm 2 50mm 2 0mm 2 t jmax 07572-036 figure 36 . junction temperature vs . total power dissipation, t a = 50c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 total power dissipation (w) 145 135 125 115 105 95 85 75 junction temperature (c) 65 500mm 2 50mm 2 0mm 2 t jmax 07572-037 figure 37 . junction temperature vs . t otal power dissipation, t a = 65c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 total power dissipation (w) 135 95 105 115 125 junction temperature (c) 85 500mm 2 50mm 2 0mm 2 t jmax 07572-038 figure 38 . junction temperature vs . total power dissipation, t a = 85c 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.2 2.0 2.4 total power dissipation (w) 140 20 60 100 40 80 120 junction temperature (c) 0 t b = 25c t b = 50c t b = 65c t b = 85c t jmax 07572-039 figure 39 . junction temperature vs . total power dissipation and board temperature
adp220/ADP221 data sheet rev. h | page 16 of 20 printe d circuit board (pcb) layout consideration s heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the adp220/ADP221 . however, as shown in table 6 , a point of diminishing ret urns eventually is reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. place the input capacitor as close as possible to the vin and gnd pins. place the output capacitor s as close as possible to the v out 1 , vout2 , and gnd pins. use 0402 or 0603 size capacitors and resistors to achieve the smallest possible footprint solution on boards where area is limited. 07572-040 figure 40 . example of pcb layout, top side 07572-041 figure 41 . example of pcb layout , bottom side
data sh eet adp220/ADP221 rev. h | page 17 of 2 0 outline d imensions 1 1-08-2012-b a b c 0.675 0.595 0.515 0.380 0.355 0.330 0.270 0.240 0.210 1.000 0.950 0.900 1.500 1.450 1.400 1 2 bot t om view (bal l side up) t o p view (bal l side down) side view 0.345 0.295 0.245 1.00 ref 0.50 bsc bal l a1 identifier se a ting plane 0.50 bsc coplanarity 0.075 figure 42 . 6 - ball wafer level chip scale package [wlcsp] (cb - 6 - 2) dimensions show in millimeters 0.50 ref 1.00 ref 1.50 1.46 1.42 1.00 0.96 0.92 0.50 ref a 1 2 b c t o p view (bal l side down) bot t om view (bal l side up) bal l a1 identifier 08-15-2012- a 0.225 nom 0.09 nom 0.330 0.315 0.300 end view 0.200 0.170 0.140 coplanarity 0.05 nom se a ting plane figure 43 . 6- ball bumped bare di e sales [bumped_chip] (cd - 6- 7) dimensions show in millimeters
adp220/ADP221 data sheet rev. h | page 18 of 20 ordering guide model 1 temperature range v out1 /v out2 output voltage (v) 2 package description package option branding adp220acbz - 1118r7 ? 40c to +125c 1.1/1.8 6 - ball wafer level chip scale pac kage [wlcsp] cb - 6 - 2 lfy adp220acbz - 1812r7 ? 40c to +125c 1.8/1.2 6 - ball wafer level chip scale package [wlcsp] cb - 6 - 2 lek adp220acbz - 1827r7 ? 40c to +125c 1.8/2.7 6 - ball wafer level chip scale package [wlcsp] cb - 6 - 2 leh adp220acbz - 2623r7 ? 40c to +125 c 2.6/2.3 6 - ball wafer level chip scale package [wlcsp] cb - 6 - 2 lgd adp220acbz - 26235r7 ? 40c to +125c 2.6/2.35 6 - ball wafer level chip scale package [wlcsp] cb - 6 - 2 l9l adp220acbz - 2812r7 ? 40c to +125c 2.8/1.2 6 - ball wafer level chip scale package [wlcs p] cb - 6 - 2 l8 w adp220acbz - 2818r7 ? 40c to +125c 2.8/1.8 6 - ball wafer level chip scale package [wlcsp] cb - 6 - 2 lel adp220acbz - 2827r7 ? 40c to +125c 2.8/2.7 6 - ball wafer level chip scale package [wlcsp] cb - 6 - 2 l8 x adp220acbz - 2828r7 ? 40c to +125c 2.8/2.8 6 - ball wafer level chip scale package [wlcsp] cb - 6 - 2 l8 y adp220acbz275275r7 ? 40c to +125c 2.75/2.75 6 - ball wafer level chip scale package [wlcsp] cb - 6 - 2 l8z adp22 0 acbz - 3033 r7 ? 40c to +125c 3.0/3. 3 6 - ball wafer level chip scale package [wlcsp] cb - 6 - 2 lh4 adp220acbz - 1212r7 ? 40c to +125c 1.2/1.2 6 - ball wafer level chip scale package [wlcsp] cb - 6 - 2 llt adp220acbz - 2525r7 ? 40c to +125c 2.5/2.5 6 - ball wafer level chip scale package [wlcsp] cb - 6 - 2 llu ADP221 acbz 2828 -r7 ? 40c to +125c 2.8/2.8 6 - ball w afer level chip scale package [wlcsp] cb - 6 - 2 l90 ADP221 acbz - 1818 - r7 ? 40c to +125c 1.8/1.8 6 - ball wafer level chip scale package [wlcsp] cb - 6 - 2 lj0 ADP221 acdz - 1818 -r7 ? 40c to +125c 1.8/1.8 6 - ball bumped bare die sales [bump chip] cd - 6 - 7 lj0 adp220 - 28 28 - evalz ? 40c to +125c 2.8/2.8 2.8 v/2.8 v evaluation board ADP221 - 2828 - evalz ? 40c to +125c 2.8/2.8 2.8 v/2.8 v with output discharge evaluation board 1 z = rohs compliant part. 2 for additional voltage options, contact a local analog devices sales or distribution representative .
data sh eet adp220/ADP221 rev. h | page 19 of 20 notes
adp220/ADP221 data sheet rev. h | page 20 of 20 notes ? 2008 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07572 - 0 - 1/13(h)

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